(1) Field of the Invention
The present invention relates to a jitter suppressing circuit, and more particularly, to a jitter suppressing circuit for suppressing jitter generated in a multistate quadrature amplitude modulation (QAM) type modulator or demodulator used in a multiplex radio apparatus, CATV and the like.
(2) Description of the Related Art
There is a demand for a smaller-sized, lower-cost transmitter and receiver of multistate quadrature amplitude modulation type used in a multiplex radio apparatus, CATV, etc. In cases where a frequency converting section in particular is reduced in size and cost, however, the oscillation frequency accuracy of a local oscillator very often lowers, deteriorating the carrier wave. Such deterioration of the carrier wave is called carrier jitter (hereinafter merely referred to as "jitter") and indicates variations of the carrier wave with time. The jitter causes reduction in the line quality, and the larger the number of states of QAM, the greater the adverse influence. The present invention relates to a jitter suppressing circuit for suppressing such jitter.
As an example of a conventional jitter suppressing circuit, FIG. 13 shows a demodulating circuit to which the jitter suppressing circuit is applied. In the demodulating circuit shown in FIG. 13, a mixing section (MIX) 11 performs quadrature detection on a modulated wave (DEM) and outputs I- and Q-phase signals to roll-off filters 12 and 13, respectively. The roll-off filters 12 and 13 shape the waveforms of the respective I- and Q-phase signals. Based on the I- and Q-phase signals whose waveforms have been shaped, a carrier reproduction control section (CR/CONT) 14 detects a phase error of the reproduced carrier wave, and a low-pass filter 15 extracts a low-frequency component from the phase error and supplies the same to a voltage control oscillator 16. The voltage control oscillator 16 reproduces a carrier wave with a frequency corresponding to the output of the low-pass filter 15, and supplies the same to the mixing section 11.
In the jitter suppressing circuit, based on the I- and Q-phase signals supplied from the demodulating circuit and containing jitter, a control section (CONT) 17 obtains a signal point specified by the I- and Q-phase signals, and detects a phase difference .theta. between this signal point and an original signal point (ideal signal point) closest thereto. An integrator 18 performs time integration on the phase difference .theta. detected by the control section 17 to remove a noise component therefrom, and supplies the resulting phase difference, or a phase difference .THETA., to a phase shifter 21.
Delay elements 19 and 20 for providing a delay of a predetermined time are arranged at a stage preceding the phase shifter 21, and respectively delay the I- and Q-phase signals, which are supplied from the demodulating circuit and contain jitter, by a predetermined period of time. The phase shifter 21 then corrects the phase of the signal point specified by the I- and Q-phase signals by the phase difference .THETA. output from the integrator 18. This phase correction serves to suppress jitter.
To carry out the phase correction, the phase shifter 21 makes calculations indicated by the following equations (1a) and (1b): EQU I.sub.O =I.sub.I .times.cos .THETA.-Q.sub.I .times.sin .THETA.(1a) EQU Q.sub.O =Q.sub.I .times.cos .THETA.+I.sub.I .times.sin .THETA.(1b)
In the equations, I.sub.I and Q.sub.I respectively represent the I- and Q-phase signals before the jitter suppression which are input to the phase shifter 21, and I.sub.O and Q.sub.O respectively represent the I- and Q-phase signals after the jitter suppression which are output from the phase shifter 21.
FIG. 14 illustrates the internal arrangement of the phase shifter 21 for making the above calculations by means of hardware. In FIG. 14, a ROM 30 is a memory for storing data cos.THETA. and sin.THETA. at its data storage locations with addresses .THETA., and when supplied with the phase difference .THETA. from the integrator 18, it outputs cos.THETA. and sin.THETA. corresponding to .THETA.. The data cos.THETA. is supplied to multipliers 31 and 34, while the data sin.THETA. is supplied to multipliers 33 and 36. The I-phase signal (I.sub.I) before the jitter suppression, which is input to the phase shifter 21, is supplied to the multipliers 31 and 36, while the Q-phase signal (Q.sub.I) before the jitter suppression, which also is input to the phase shifter 21, is supplied to the multipliers 34 and 33. The product obtained by the multiplier 31 is supplied to a subtractor 32, and the product obtained by the multiplier 33 is also supplied to the subtractor 32. The subtractor 32 subtracts the product of the multiplier 33 from the product of the multiplier 31 and outputs the resulting difference as the I-phase signal (I.sub.O) after jitter suppression. Similarly, the product obtained by the multiplier 34 is supplied to an adder 35, and the product obtained by the multiplier 36 is also supplied to the adder 35. The adder 35 adds these products together and outputs the resulting sum as the Q-phase signal (Q.sub.O) after jitter suppression.
FIG. 15(A) illustrates the internal arrangement of the control section 17. Specifically, the control section 17 comprises a ROM 37. The ROM 37 has data storage locations with two-dimensional addresses corresponding to the I- and Q-phase signals supplied from the demodulating circuit and containing jitter, and stores phase difference .theta. data between each signal point corresponding to two-dimensional address values and a corresponding original signal point (ideal signal point) closest thereto at a corresponding data storage location thereof.
The control section 17 may alternatively comprise an arithmetic unit for calculating the phase difference .theta. according to the following equation (2): EQU .theta.=tan.sup.-1 (Q/I)-tan.sup.-1 (Q'/I') (2)
In the equation, Q and I represent the Q- and I-phase signals supplied from the demodulating circuit and containing jitter, and Q' and I' represent Q- and I-phase signals indicating an original signal point (ideal signal point) closest to the signal point specified by the I- and Q-phase signals containing jitter.
FIG. 15(B) illustrates the internal arrangement of the integrator 18. Specifically, the integrator 18 comprises an accumulator made up of an adder 38 and a flip-flop (FF) 39, and successively adds a newly input phase difference .theta. to the result of operation of the preceding symbol. Consequently, the integrator 18 integrates the phase difference .theta. supplied from the control section 17, and outputs the result to the phase shifter 21 as the phase difference .THETA..
Thus, the jitter suppressing circuit employs feedforward control in which the phase shifter 21 is operated in accordance with the phase difference .THETA. detected at the input side thereof, and this permits good follow-up performance with respect to rapid input variations with time such as jitter.
It is here assumed that the conventional demodulating circuit handles a 64-level QAM signal, as shown in FIG. 16. It is also assumed that a signal point which should originally coincide with a signal position P1 is shifted to a signal position P2 due to jitter. In this case, the jitter suppressing circuit locates the signal position P1 which is an ideal signal point closest to the signal position P2, and detects a phase difference .theta.1 from the ideal signal position P1. Based on this phase difference .theta.1, jitter is suppressed and the signal position P2 is shifted to the signal position P1 as the ideal signal point.
If, however, jitter is so large that a signal point which should originally coincide with the signal position P1 is shifted to a signal position P3, then a signal position P4 which is another ideal signal point is closest to the signal position P3. Accordingly, the jitter suppressing circuit, which should originally detect a phase difference .theta.2, detects a phase difference .theta.3 from the signal position P4 as the ideal signal point, and suppresses jitter based on this phase difference .theta.3. As a result, jitter is not reduced at all but is enlarged, causing a bit error.